The invention lies in the integrated technology field. More specifically, the invention relates to a method of fabricating an integrated circuit, in which semiconductor elements, in particular transistors of at least a first conductivity type, are fabricated with the aid of spacer technology on a substrate. In the process, a spacer material is applied and then partially etched back so that spacers remain. Then, a mask is placed and a first doping is introduced into the substrate, and the spacers are subsequently etched back.
Such methods are used for fabricating integrated circuits with a multiplicity of transistors or other switching elements in which spacers are temporarily produced in order, for example, to protect regions of the substrate surface which adjoin gate structures against a doping that is to be introduced. Transistors of CMOS technology, in particular, have lightly doped LDD regions in comparison with source and drain on both sides of the gate electrode, the regions being protected by spacers made, for example, of polysilicon during the doping of source and drain. After the spacers have been removed, the weaker doping for the LDD regions is introduced.
Integrated circuits have further semiconductor elements in addition to transistors and diodes. These include, in particular, passive components such as resistors and capacitors. Capacitors can be incorporated, by way of example, between two metallization planes. In that case only low-temperature dielectrics with a low breakdown field strength can be used. In analog or partly analog, partly digital integrated circuits, however, higher-quality capacitors having e.g. a thermal oxide as the dielectric and having electrodes made of polysilicon are required. Such capacitors can be fabricated during the patterning of the gate electrode of the transistors. In that case, the gate oxide layer simultaneously serves as the capacitor dielectric and the gate layer made of polysilicon simultaneously serves as the capacitor electrode. The second capacitor electrode is formed by the substrate. In those gate-substrate capacitors, however, the substrate potential is coupled to the potential of the gate electrode, resulting in considerable circuitry problems. Therefore, both electrodes are produced from polysilicon in higher-quality capacitors. In that case, the gate electrode made of polysilicon is utilized as the first capacitor electrode and e.g. the post-oxide (or a separately deposited insulator layer) situated thereabove is utilized as the dielectric. A second layer of polysilicon is deposited over that to fabricate the second capacitor electrode.
In technologies with a diffusion-doped gate layer, resistive tracks made of polysilicon can also be produced only with an additional layer made of polysilicon and subsequent doping, if the sheet resistivity is intended to be freely selectable. Conventional integrated circuits having, at least in part, analog functions are thus always fabricated in such a way that after the completion of the transistors or diodes, the capacitors and resistors are produced during additional process steps.
However, each additional process step leads to a considerable increase in the fabrication costs, and, in the face of these cost disadvantages, high-quality passive components made of polysilicon are frequently dispensed with.
In contrast with the technology disclosed in U.S. Pat. No. 5,391,906 and European patent application EP 880 165 A1, for instance, the present invention is based on the spacer technology as it is described for instance in Widmann: Technologie hochintegrierter Schaltungen [Technology of Large-Scale Integrated Circuits], Springer Verlag, 1996.
The object of the invention is to provide a method of fabricating integrated circuits which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which makes it possible to fabricate integrated circuits having active and passive components with the least possible additional outlay for the production of the passive components, under certain circumstances also of further active components.
With the above and other objects in view there is provided, in accordance with the invention, a method of fabricating an integrated circuit, wherein semiconductor elements, such as transistors, are formed on a substrate with the aid of spacer technology. The method comprises the following method steps:
applying a spacer material on a substrate;
covering the spacer material with an auxiliary layer and placing an auxiliary mask on the auxiliary layer;
partially etching back the auxiliary layer and the spacer material to form useful elements covered by the auxiliary layer and spacers and subsequently removing the auxiliary mask;
masking with a mask and introducing a first dopant into the substrate; and
etching back the spacers selectively with respect to the auxiliary layer and the useful elements covered thereby.
The invention exploits the fact that polysilicon is already applied during the production of the spacers which are necessary for fabricating the transistors. The polysilicon has, however, hitherto been almost completely removed again by anisotropic etching. Only the spacers remaining at the gate edges are used for transistor fabrication.
The invention utilizes the spacer technology employed in the context of transistor fabrication. In this technology, spacer material is first applied and then partially etched back, so that spacers remain. The substrate is subsequently masked by a mask and a first doping is introduced. Afterwards, the spacers are etched back, that is to say removed.
According to the invention, the generic method is extended as follows: after the application of the spacer material, the latter is covered with an auxiliary layer; an auxiliary mask is applied to said auxiliary layer; the auxiliary layer is etched back at the locations which are not covered by the auxiliary mask, in the same way as spacer material is etched back, after which the auxiliary mask is removed again; and the spacers are etched back or removed selectively with respect to the auxiliary layer. Although the auxiliary layer used according to the invention is etched back at the locations which are not covered by the auxiliary mask, in the same way as the underlying spacer material is etched back, the structures made of spacer material which are produced through the auxiliary mask are nonetheless subsequently protected by the auxiliary layer during the process of completely and selectively etching back the spacers. As a result polysilicon structures remain after the removal of the spacers, and can be utilized for producing the high-quality capacitors and resistors. Additional process steps for applying layers after the completion of the transistors, in particular after the introduction of the dopings are no longer necessary. The layer structures required for the passive components are instead produced simultaneously in the context of the spacer technology employed. Moreover, with the aid of the polysilicon applied during the spacer deposition, it is possible to produce further active components, e.g. transistors with a thicker gate oxide.
With the method according to the invention, the process blocks for fabricating the transistors, on the one hand, and the passive components, on the other handxe2x80x94the process blocks originally being carried out separately in timexe2x80x94are interwoven to form a single process block which, by comparison with the process block for fabricating the transistors, merely has three additional process steps, namely the application of the auxiliary layer, the application of the auxiliary mask and the removal of the auxiliary mask. The combination of these process steps with those which, in the context of transistor fabrication, can simultaneously be utilized for fabricating the passive components and the further transistors results in a short process sequence and thus a cost-effective method for fabricating analog or partly analog integrated circuits.
The method according to the invention is derived from a method for fabricating transistors, but it is not restricted to these components, rather is suitable for any application in which spacers or other dummy structures are produced, the material applied in order to produce them is firstly removed partially, that is to say except for the dummy structure, and later the dummy structure itself is likewise removed.
In the context of fabricating transistors of at least a first conductivity type, a preferred embodiment provides a further step of masking and introducing a weak, second doping, for the purpose of producing LDD regions.
In order to produce transistors of a second conductivity type, opposite to the first conductivity type, a further embodiment provides the additional steps of masking and introducing a third doping for the purpose of producing source and drain regions, etching back further spacers and also masking and introducing a weak; fourth doping for the purpose of producing further LDD regions. It is expediently provided that during the introduction of the first and/or third doping, in addition to the source and drain terminals, useful elements such as low-value resistors or capacitor electrodes are doped at the same time.
In accordance with a development of the invention, a weak doping for the purpose of producing high-value resistors is introduced into the applied auxiliary layer before the auxiliary layer is masked by the auxiliary mask.
An alternative embodiment provides for useful elements serving as high-value resistors to be doped at the same time during the doping steps for producing LDD regions.
Preferred embodiments provide for the spacers to be etched back anisotropically, for the spacer material to be polysilicon, for the auxiliary layer to be pervious to dopings, for the auxiliary layer to be a hard mask, preferably an oxide such as silicon oxide, and the mask to be a resist mask.
In accordance with the use of the generic method for fabricating transistors, further embodiments provide for initially a first gate oxide, a first gate layer and a further oxide, the so-called post-oxide, to be produced, and for the capacitors to be formed from the first gate layer, the post-oxide and the spacer material.
In accordance with another feature of the invention, further useful elements include gate layers of further transistors with a thicker gate oxide, which is composed of the first gate oxide, the post-oxide and the spacer material deposited.
In accordance with again another feature of the invention, the process of etching back the spacers is also effected selectively with respect to the post-oxide.
In accordance with a concomitant feature of the invention, it may be provided that during processing of the useful elements, a layer protected by a foundation layer located under the spacer material is covered laterally, and protected, by the spacers.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating integrated circuits having transistors and further semiconductor elements, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.